This invention relates, in general, to fixtures for testing unencapsulated integrated circuits and, more specifically, to an interface probe card manufactured from semiconductor materials.
The manufacture of semiconductor integrated circuits entails a multitude of procedures including: design, process, packaging, and test. What is more, testing has been divided into functional, parametric and burn-in methodologies. In each of these regimes the devices may be tested in wafer, die or packaged form. And, although packaging is a comparatively expensive step, semiconductor manufacturers have packaged the devices prior to testing; hence, prior to ensuring proper device operation. Now, however, the high cost of packaging semiconductor devices, coupled with the increased complexity of the semiconductor device structures, requires that devices be tested in wafer or die form in order to decrease the probability of packaging nonoperational units. Further, with the advent of multichip modules, wafer or die level testing is required since the semiconductor device is only one of several components mounted on a multichip carrier.
A fixed probe board for testing semiconductor wafer chips was disclosed by Hasegawa in U.S. Pat. No. 4,563,640. The probe board comprises a multiplicity of probe needles mounted to a support base. The configuration of the probe needles matches an array of electrode pads spread around the periphery of the integrated circuit to be tested. Although this invention has provided a means for testing unencapsulated integrated circuits it had several drawbacks. First Hasegawa's fixed probe board is impractical for parallel testing more than four integrated circuits in die or wafer form. Second, semiconductor manufacturers have started to design integrated circuits with the array of electrode pads spread across the surface area (referred to as an area array) of the integrated circuit rather than around the periphery; this technique can not be used for large numbers of electrode pads configured in an area array. Third, the difference between the coefficients of thermal expansion of the probe board and the device under test may result in a high impedance contact between the probe needles and the electrode pads on the semiconductor device. In fact, the probe needles and device electrode pads may separate completely, forming an electrical "open." Finally, the probe needles are fragile and require frequent re-alignment.
B. Leslie and F. Matta, in their paper "Membrane Probe Card Technology," presented at the 1988 International Test Conference, addressed the limitations of conventional probe cards. Moreover, these researchers have described a probe card wherein the probe needles were replaced with contact bumps formed on a flexible dielectric membrane. Further, a microstrip transmission line, formed on one side of the membrane, connects test circuitry with the device under test. Since the conductor traces and the contact bump positions are obtained using photolithographic techniques, integrated circuits with electrode pads in either a peripheral or area array can be tested. Moreover, the relative positions of contact bumps and traces are defined by the photolithographic steps thereby, eliminating the need for any "re-alignment." In addition, the flexibility of the membrane allows contact with nonplanar surfaces as well as decreases damage to electrode pads on the device under test. Still, this technique did not eliminate the thermal mismatch inherent in using a probe card made from a different material than the device being tested. Accordingly, it would be beneficial to have a readily manufacturable interface probe card capable of reliably contacting electrode pads in either a peripheral or array configuration, and which has thermal properties similar to the device under test.